<div class="content-intro"><h2>About FuriosaAI </h2> <p>FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&amp;D lab in Lisbon.&nbsp;</p> <p>Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence&nbsp; for every enterprise.</p></div><p></p> <h2 data-pm-slice="0 0 []">About the Role</h2> <p>We're looking for a Senior Emulation Engineer to join our hardware verification team. In this role, you'll own the emulation environment for our next-generation NPU — from platform bring-up to full-system integration — and play a critical part in getting silicon right before tape-out. You'll work across time zones with engineers in Korea and the US, and have a direct impact on the quality and schedule of our most complex SoCs to date.</p> <p>&nbsp;</p> <h2>Key Responsibilities</h2> <ul> <li> <p>NPU Emulation &amp; Bring-up: Bring-up of next-generation NPUs on emulation platforms. Root-cause complex system-level test failures and resolve emulator environment challenges.</p> </li> <li> <p>Emulation Interface &amp; Memory Integration: Enable full-system NPU testing by integrating and bringing up high-speed protocol models (PCIe, Ethernet) and advanced memory subsystems (HBM/DDR) within the emulation environment.</p> </li> </ul> <p>&nbsp;</p> <h2>What We're Looking For</h2> <ul> <li> <p>Emulation Platform Expertise: Extensive, hands-on experience in developing, compiling, and deploying large-scale emulation models using industry-leading platforms such as Synopsys ZeBu and Cadence Palladium.</p> </li> <li> <p>Domain Knowledge: Deep technical understanding of AI accelerator architectures (NPU), along with expertise in one or more of the following: interconnect buses, high-speed I/O protocols (PCIe, Ethernet), and advanced memory interfaces (LPDDR, HBM).</p> </li> <li> <p>Strategic Verification Leadership: Demonstrated ability to define comprehensive emulation strategies, formulate detailed test plans, and drive verification execution for large-scale, complex SoCs.</p> </li> </ul> <p>&nbsp;</p> <h2>Minimum Qualifications</h2> <ul> <li> <p>8+ years of industry experience in hardware emulation or system-level verification.</p> </li> <li> <p>Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related engineering field.</p> </li> <li> <p>Strong domain knowledge of AI accelerator architectures (NPU), interconnect buses, high-speed I/O protocols (PCIe, Ethernet), and advanced memory interfaces (LPDDR, HBM).</p> </li> <li> <p>Ability to take initiative and work independently in a cross-regional environment, collaborating effectively across different time zones (Korea and US).</p> <p>&nbsp;</p> </li> </ul> <h2>Preferred Qualifications</h2> <ul> <li> <p>Track record of writing production-grade, meticulous test plans</p> </li> <li> <p>Strong foundational knowledge of networking protocols</p> </li> </ul> <p>&nbsp;</p> <h2>Contact</h2> <ul> <li> <p>recruit@furiosa.ai</p> </li> </ul>