<div class="content-intro"><h2>About FuriosaAI </h2> <p>FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&amp;D lab in Lisbon.&nbsp;</p> <p>Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence&nbsp; for every enterprise.</p></div><h2><strong>About the Role</strong></h2> <p>We are looking for a senior engineer to own the physical interconnect architecture of our rack-scale AI computing systems.</p> <p>This role focuses on the physical implementation of high-speed links within the rack: cables, connectors, backplanes, routing, serviceability, and high-density integration. Network topology and protocol architecture are owned by our architecture and high-speed interface teams, and SI/PI analysis is performed by our SI/PI team. This role owns the physical realization and the technical direction of connector and cable vendors.</p> <h2><strong>Key Responsibilities</strong></h2> <ul> <li>Define the physical interconnect architecture for high-density rack systems</li> <li>Define cable, connector, and backplane strategies, and evaluate DAC, AEC, AOC, and emerging interconnect technologies</li> <li>Drive trade-offs between near-package copper (NPC/MPC), co-packaged copper (CPC), and co-packaged optics (CPO)</li> <li>Define connector density, reach, routing, and serviceability requirements</li> <li>Develop removable cable and backplane architectures that support field service</li> <li>Define physical channel allocation and routing strategies across trays and switches</li> <li>Resolve mechanical conflicts among cables, connectors, cooling components, and power distribution</li> <li>Coordinate physical interconnect requirements with system, mechanical, thermal, power, and SI/PI teams</li> <li>Define DFM/DFA requirements for cable and connector assembly</li> <li>Evaluate interconnect vendors, review their technical proposals, and direct external design partners and CM/ODM teams</li> </ul> <h2><strong>Minimum Qualifications</strong></h2> <ul> <li>Extensive experience with high-speed physical interconnect systems</li> <li>Strong understanding of high-speed cables, connectors, backplanes, and physical channel design</li> <li>Experience with high-density server, data center, or networking systems</li> <li>Understanding of signal integrity considerations that drive physical interconnect architecture</li> <li>Experience working with connector and cable vendors and external design partners</li> <li>Experience taking complex interconnect systems through manufacturing</li> <li>Excellent English communication skills</li> </ul> <h2><strong>Preferred Qualifications</strong></h2> <ul> <li>Experience with 800G or higher-speed systems</li> <li>Experience with 200G/lane or next-generation SerDes</li> <li>Experience with racks carrying 1,000+ high-speed links</li> <li>Experience with OCP rack architectures<br>Experience with next-generation connector technologies, or near-package and co-packaged interconnect</li> </ul><div class="content-conclusion"><h2>Why Join FuriosaAI</h2> <p>The defining bottleneck of the AI era is building the right hardware and software stack to run it at global scale. Furiosa is solving this challenge holistically from the ground up.</p> <p>With our flagship chip, RNGD, in mass production today and our next-generation platform in development with Broadcom, we are proving that full-stack, tensor-native compute is the future of AI infrastructure. This is a pivotal moment to join our team, right as we accelerate our global expansion.</p> <p>At Furiosa, you will:</p> <p>Solve AI’s Most Urgent Challenge. Help build the high-performance, energy-efficient inference hardware and software required to fulfill the promise of advanced AI.</p> <p>Pioneer Full-Stack Co-Design. Work with teams that are architecting solutions from silicon up through the compiler (featuring innovations like Tensor Contraction Language and Virtual ISA) and serving frameworks.</p> <p>Ship Real-World Silicon, Software, and Solutions. Turn breakthrough technology into commercial deployment. RNGD is in mass production with TSMC and running live enterprise workloads for global leaders like LG AI Research and Samsung SDS.</p> <p>Partner With the Industry's Best. Collaborate across an elite global ecosystem that includes TSMC, Broadcom, SK Hynix, and GUC.</p> <p>Do Your Life’s Best Work. Join a brilliant, low-ego, mission-driven team in a high-trust environment that values autonomy, intellectual curiosity, and shared ambition.&nbsp;</p> <h2>Contact</h2> <ul> <li><a href="mailto:recruit@furiosa.ai">talent@furiosa.ai</a></li> </ul></div>