Layered architectural diagram of FuriosaAI's software stack for an AI accelerator chip. The top layer is labeled 'Serving' with details for running workloads on Furiosa AI Inference Server. The middle layer 'Furiosa Runtime' includes components furiosa-torch, furiosa-tcl, and furiosa-vISA as the runtime driver and compiler. The bottom layer shows the AI accelerator chip itself labeled 'Furiosa AI accelerator chip'.

Build at any layer, 
from model to silicon

​
Furiosa Docs

Serving

FURIOSA-LLM

furiosa-llm: drop-in, OpenAI-compatible inference

Point your existing client at a new endpoint and serve any pre-compiled model: no rewrite, no proprietary API to learn.
​
furiosa-llm docs

shell

pip install furiosa-llm
furiosa-llm serve [model]
# Serving on :8000 (OpenAI-compatible)
from openai import OpenAI

client = OpenAI(
    base_url="http://localhost:8000/v1"
)
client.chat.completions.create(model="[model]", ...)
from furiosa_llm import LLM

llm = LLM(
    model="[model]",
    dtype="[precision]",
)
out = llm.generate(prompts)
​
Go to Furiosa-LLM Docs
Model Zoo

Start from a model that already runs

OPENAI
Model zoo icon

gpt-oss

20B · 120B

FP8

Text generation

QWEN

Qwen3

4B · 8B · 32B

FP8

Text generation

UPSTAGE
star icon

Solar Open

100B

NVFp4A16

Text generation

Qwen3

4B · 8B · 32B

FP8

Text Generation

Qwen3 MoE

30B-A3B

FP8

Text Generation

Qwen3-Coder

30B-A3B

FP8

Code Generation

Qwen3-VL

2B · 4B · 32B

BF16

Vision-Language

Qwen3-Embedding

0.6B · 4B · 8B

BF16

Embedding

Qwen3-Reranker

0.6B · 4B · 8B

BF16

Reranking

gpt-oss

20B · 120B

MXFP4

Text Generation

Gemma 4

31B

FP8

Vision-Language

Solar Open

100B

NVFP4A16

Text Generation

K-EXAONE

236B-A23B

NVFP4A16

Text Generation

EXAONE 4.5

33B

FP8

Vision-Language

EXAONE 4.0

32B

FP8

Text Generation

EXAONE 3.5

7.8B · 32B

BF16

Text Generation

Mistral NeMo

12B

FP8

Text Generation

Llama 3.3

70B

FP8 · INT8 · BF16

Text Generation

Llama 3.1

8B

FP8 · BF16

Text Generation

DeepSeek-R1-Distill

7B · 8B · 14B · 32B · 70B

BF16

Reasoning

QwQ

32B

BF16

Reasoning

Qwen2.5

0.5B · 7B · 14B · 32B

BF16

Text Generation

Qwen2.5-Coder

7B · 14B · 32B

BF16

Code Generation

BGE-M3

0.6B

BF16

Embedding

BGE-Reranker-v2-M3

0.6B

FP32

Reranking

E5-Mistral

7B

FP16

Embedding

Harrier-OSS-v1

0.6B

BF16

Embedding

Qwen3.6

27B · 35B-A3B

FP8

Vision-Language

Qwen3.5

0.8B

BF16

Vision-Language

Showing 6 of 32

DEPLOYING

EASY DEPLOYMENT

Pick the deployment path that fits your needs

Gray square icon with three horizontal server-like bars and the text 'Bare Metal' underneath on a black background with a subtle grid pattern.
BARE METAL

A dedicated NXT RNGD Server, hosted at a data center near you.

Gray square block with a cloud icon embossed above the text 'API Endpoint' on a black grid background.
API ENDPOINT

Call models served on RNGD through our cloud partners. Nothing to install.

PROGRAMMING

FURIOSA-TORCH

Move your model to RNGD with furiosa-torch

Bring your own PyTorch model, including ones not in the model zoo. furiosa-torch adds RNGD as a PyTorch device: run it as-is (eager mode) while you develop, compile it with torch.compile for performance, or build it ahead of time for deployment.
① Move to the device

python

import torch, furiosa.torch

device = torch.device("furiosa:0")
model = MyModel().to(device)
② Run it your way — three paths, one backend

Eager

torch.compile

Ahead-of-time

out = model(x.to(device))                  # eager: ops run as dispatched

compiled = torch.compile(model, backend=furiosa.torch.backend)
out = compiled(x.to(device))               # whole-graph compile

runnable = CompileModule.from_module(model, inputs)  # AOT → Runnable
FURIOSA-TCL / FURIOSA-VISA

Two levels of kernel programming

COMING Q4 2026

TCL

Tensor Contraction Language

Declare what to compute over named symbolic axes. Kernels are generic over shape; the compiler owns tiling, layout and scheduling.

python

import furiosa.tcl as tcl

@tcl.kernel
def linear(x: tcl.bf16[M, K], w: tcl.bf16[N, K]) -> tcl.f32[M, N]:
    # axes missing from the output are contracted away
    return tcl.operation.contract(x, w, out=[M, N])
COMING Q4 2026

vISA

TCP Virtual ISA

Hand-optimize the hot path. Reason in tensors while directly managing memory placement and Tensor Unit scheduling.

rust

#[device(chip=1)]
fn gemm(a: DmTensor<bf16, m![M, K]>,
        b: DmTensor<bf16, m![K, N]>) -> DmTensor<f32, m![M, N]> {
    // you choose the memory tier and the schedule
    a.fetch().contract(b).commit()
}

Dive Deeper

Title page of a document titled 'TCP: A Tensor Contraction Processor for AI Workloads' with a list of multiple authors from Furiosa AI, INESC-ID / Instituto Superior Técnico, University of Lisbon, and Seoul National University.
​
TCP paper, ISCA 2024
Download the peer-reviewed architecture paper.
Download the TCP paper
Text reading 'Furiosa Renegade Renegade 2026 Summit, Seoul KR' over a dynamic red abstract background.
​
Keynote: hardware and software design philosophy
Our CTO and CRO go deep on why the primitive is a tensor contraction and what that does to the compiler.
Watch the keynote
Logo with the words 'HOT CHIPS'; 'HOT' is in bold red uppercase letters with flame designs below, and 'CHIPS' is in black uppercase letters spaced below a black line with vertical ticks resembling a ruler.
​
Hot Chips talk by CEO June Paik
The full RNGD presentation from Hot Chips 2024.
Watch the Hot Chips talk