<div class="content-intro"><h2>About FuriosaAI </h2> <p>FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&amp;D lab in Lisbon.&nbsp;</p> <p>Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence&nbsp; for every enterprise.</p></div><h2><strong>About the Job</strong></h2> <p>In AI infrastructure, the unit of "the computer" is already the rack. Accelerators have moved into compute trays, switches into switch trays, and power into the rack's power shelves, with Ethernet connecting all of it. Powering this computer on, configuring it, watching over it, and fixing it is the job of the rack management system. Scale-up networking is also converging on open Ethernet standards such as OCP ESUN, SUE-T, and UEC.</p> <p>FuriosaAI is building an Ethernet-based scale-up system that connects many AI accelerators so they work as one large accelerator. Our goal goes beyond the performance of individual links: we want performance and stability when the AI accelerators, host software, switch fabric, and the rack's power and management systems all work together.</p> <p>We have brought up links on Ethernet endpoints, validated the switch fabric, and studied how inference workloads behave when LLM weights held in remote memory are read over Scale-Up Ethernet. Now we are moving to <strong>building and validating a single rack as a complete system, aligned with open rack standards</strong>.</p> <p>In this role, you will configure Ethernet endpoints and switches, understand how network operating systems (NOS) behave, and analyze the root causes of performance degradation and errors that appear under real workloads. You will look across hardware, firmware, software, and fabric to isolate problems, and work with engineers in each area to fix them. You will also build a rack management system that handles nodes, switches, and power as one, along with observability, failure detection, and test automation, so that racks can be brought up, operated, and validated repeatably and reliably.</p> <p>We work alongside AI agents. We split device bring-up, builds, long-running tests, log analysis, and documentation across multiple agents, so engineers can focus on deciding what to test and judging the results.</p> <p>Rather than depth in a single field, we are looking for an engineer who moves across networking, switch OS, rack hardware, system management, and AI workloads, and <strong>sees the whole rack as one computer</strong>.</p> <h2><strong>Key Responsibilities</strong></h2> <ul> <li><strong>Scale-Up Ethernet endpoint and SoC integration validation:</strong> Validate the scale-up Ethernet endpoint (controller IP) built into our accelerator SoC, from pre-silicon prototypes through silicon. Understand how the endpoint works with the SoC's on-chip interconnect (AXI), DMA, memory map, interrupts, and firmware, and follow problems past the link into the chip, resolving them with RTL and firmware engineers.</li> <li><strong>NIC and switch fabric tuning:</strong> Building on an understanding of how the switch NOS behaves, configure NICs and switches for the traffic profile, and validate scale-up link-layer behavior such as <strong>buffers, queues, PFC, LLR, and CBFC</strong> to improve performance and stability under congestion. Evaluate the latest purpose-built scale-up switches.</li> <li><strong>Cross-layer root-cause analysis:</strong> Reproduce data-transfer errors and performance bottlenecks using packet captures, device counters, logs, and telemetry, and isolate the cause to hardware, firmware, driver, software, or fabric.</li> <li><strong>Evaluation with real AI workloads:</strong> Build clusters that run collective communication (all-reduce, all-to-all) and LLM inference and training traffic to find issues and corner cases that lab tests miss. Measure bandwidth, latency (including tail latency), and stability, and verify the effect of configuration changes and catch performance regressions.</li> <li><strong>Link and interoperability validation:</strong> Analyze MAC/PCS/FEC/SerDes status and error counters, and validate link stability and interoperability across combinations of optical modules (DR, FR, etc.), DAC/AEC/AOC cables, and switch ports. Use CMIS to check each module's application mode, firmware version, temperature, and optical power, and verify that links stay stable through repeated resets and temperature changes.</li> <li><strong>Rack and fabric management design and build-out:</strong> Bring node BMCs, switches, power shelves/BBUs, PDUs, and cooling under one rack manager that handles inventory (devices, FRUs, firmware, optical modules), power sequencing and remote control, and firmware updates. Use standard interfaces (Redfish and PLDM for nodes, gNMI/YANG for switches), and define the API exposed to the upper-level orchestrator with reference to OCP specifications such as OpenRMC. Also design scale-up fabric management functions such as endpoint identity and address assignment, topology discovery, link bring-up ordering, and domain partitioning.</li> <li><strong>Rack-level observability and reliability validation:</strong> Observe power, thermal, link (per-lane FEC), optical module, and device health in one place as time series, design failure detection, isolation, fail-safe recovery scenarios, and RAS (Reliability, Availability, Serviceability), and verify them with fault injection.</li> <li><strong>Scale-Up Ethernet rack system build and validation:</strong> Build racks from compute trays (with NPUs and NICs), switch trays, power shelves, a management network, and the DAC, AEC, AOC, and optical cabling that connects them, and validate them stage by stage from link bring-up to full rack integration. Lead the PoC that moves our current rack validation environment to OCP-standard configurations such as Open Rack.</li> <li><strong>Validation infrastructure and automation:</strong> Automate remote console and power (PDU) control, test execution, and result collection, and build dashboards and technical documentation for long-duration stability testing and regression validation.</li> <li><strong>AI agent–driven work orchestration:</strong> Delegate device bring-up, builds, test execution, log analysis, and documentation to AI agents such as Claude Code and Codex, and design the foundations (equipment reservation and locking, remote-control APIs, job queues) that let many agents share lab equipment without conflicts. Check agent output against evidence, raising both the speed and the quality of decisions.</li> <li><strong>Standards and ecosystem:</strong> Bring developments from OCP (ESUN, Open Rack, Hardware Management), UEC, the SONiC Scale-Up WG, and other standards bodies into our designs, and work with switch, power, BMC, and test-equipment vendors.</li> </ul> <h2><strong>Minimum Qualifications</strong></h2> <ul> <li>BS in Computer Science, Electrical Engineering, or a related field, or equivalent practical experience</li> <li>Understanding of how data-center Ethernet networks work (switches, lossless/RDMA), and experience configuring and debugging network devices or systems on Linux</li> <li>Experience developing or debugging semiconductor system software that works with hardware at the register and memory-map level (e.g., SoC firmware, device drivers, silicon bring-up and diagnostic software)</li> <li>Hands-on experience with bring-up, integration testing, or performance analysis of rack- or cluster-scale systems that combine servers, switches, and accelerators</li> <li>Ability to automate test execution, device control, and log collection with Python or shell scripts</li> <li>Active use of AI tools (LLMs, coding agents) in day-to-day work, and the ability to verify their output against evidence</li> <li>Ability to form hypotheses from evidence such as packets, logs, and performance counters, and to narrow down root causes through reproducible experiments</li> <li>Ability to collaborate with engineers from different disciplines and to document test methods and results clearly</li> </ul> <h2><strong>Preferred Qualifications</strong></h2> <ul> <li>Experience with link bring-up, performance evaluation, or interoperability testing in 100G–800G high-speed Ethernet environments</li> <li>Understanding of or hands-on experience with MAC/PCS/FEC/SerDes, QSFP-DD/OSFP optical modules and DAC/AEC/AOC cables, and CMIS-based module management</li> <li>Experience designing rack-scale copper (DAC/AEC) and optical (AOC, optical modules) cabling, or qualifying cables and modules, including interoperability testing across vendors and manufacturing lots</li> <li>Experience configuring lossless Ethernet fabrics and tuning congestion control, including PFC, ECN, buffers, and queues</li> <li>Understanding of switch NOS architecture and behavior, and experience with Broadcom Tomahawk-family switches</li> <li>Experience analyzing performance bottlenecks in DMA, remote memory access, and collective communication (all-reduce, all-to-all) on NPU/GPU accelerator systems</li> <li>Experience validating the interaction between an Ethernet controller IP and the SoC (on-chip interconnect, DMA, memory subsystem), or tracking down issues at the C/C++ and RTL level together with driver, firmware, and hardware engineers</li> <li>Experience with rack and server management using BMC/OpenBMC, Redfish, PLDM/MCTP, or OpenRMC (inventory, firmware updates, power and thermal control, failure recovery), or experience developing and operating a rack manager or fleet management system</li> <li>Experience building hardware test labs, CI-based regression testing, telemetry, or long-duration stability test infrastructure</li> <li>Experience building and running workflows that split work across multiple AI agents (e.g., device-control APIs for agents, session and job management, result-verification harnesses)</li> <li>Experience with OCP rack hardware such as Open Rack (ORv3/ORW), 48 V and 800 VDC power, power shelves, and BBUs, or with bringing up racks together with ODMs</li> <li>Understanding of scale-up standards such as OCP ESUN/SUE-T, UEC (LLR, CBFC), and UALink, or participation in the OCP or SONiC communities</li> </ul><div class="content-conclusion"><h2>Why Join FuriosaAI</h2> <p>The defining bottleneck of the AI era is building the right hardware and software stack to run it at global scale. Furiosa is solving this challenge holistically from the ground up.</p> <p>With our flagship chip, RNGD, in mass production today and our next-generation platform in development with Broadcom, we are proving that full-stack, tensor-native compute is the future of AI infrastructure. This is a pivotal moment to join our team, right as we accelerate our global expansion.</p> <p>At Furiosa, you will:</p> <p>Solve AI’s Most Urgent Challenge. Help build the high-performance, energy-efficient inference hardware and software required to fulfill the promise of advanced AI.</p> <p>Pioneer Full-Stack Co-Design. Work with teams that are architecting solutions from silicon up through the compiler (featuring innovations like Tensor Contraction Language and Virtual ISA) and serving frameworks.</p> <p>Ship Real-World Silicon, Software, and Solutions. Turn breakthrough technology into commercial deployment. RNGD is in mass production with TSMC and running live enterprise workloads for global leaders like LG AI Research and Samsung SDS.</p> <p>Partner With the Industry's Best. Collaborate across an elite global ecosystem that includes TSMC, Broadcom, SK Hynix, and GUC.</p> <p>Do Your Life’s Best Work. Join a brilliant, low-ego, mission-driven team in a high-trust environment that values autonomy, intellectual curiosity, and shared ambition.&nbsp;</p> <h2>Contact</h2> <ul> <li><a href="mailto:recruit@furiosa.ai">talent@furiosa.ai</a></li> </ul></div>